Plenary Speaker 1: Howard Heck
Principal Engineer, Intel Corporation
The USB Type-C Connector: A Brave New World for the PC Industry
Abstract: The introduction of the USB Type C connector promises to realize the vision of a single, user friendly connector for all computers (smartphones, tablets, laptops, etc.) and for all I/O (USB, display, etc.): by delivering a great experience for the end user in which he/she plugs a device into a computer and it just works no matter what…
- I/O interface (e.g. USB, Display Port)
- connector orientation (i.e. flappable)
- end of the cable (no distinction between host and device)
Realizing the vision requires that significant complexity including selection of I/O interface, identifying connector orientation, resolving host/device roles and sourcing/syncing of power, be handled seamlessly without user intervention. Needless to say, this creates a number of significant challenges in the design of Type C-based products. This talk will provide an introduction to the technical challenges that the industry faces, discuss the current directions for addressing them and will point out some opportunities for innovation in realizing the Type C vision.
Presenter: Howard is a Principal Engineer at Intel, specializing in signal integrity. In his 30 years in the industry he has held various technical and management positions related to computer system design and manufacturing. His most recent responsibilities include the development of specifications and product solutions for Universal Serial Bus 3.0/3.1. The responsibilities span from initial spec development to post-silicon validation. He co-authored “Advanced Signal Integrity for High-Speed digital Designs”, a graduate level textbook on signal integrity, and from 1998 through 2009 taught signal integrity at the Oregon Graduate Institute. He is an IEEE senior member and is the chair for the IEEE Oregon joint CPMT-CAS chapter. He has 12 patents with 21 others pending.
Workshop 1: A Simple Method to Characterize and Accurately Remove the Effects of Push-on Connectors
Application Engineer, Keysight Technologies
Abstract: Push-on (blind mate) connectors are commonly used in SI fixture design and device connectivity. They are made by a variety of manufacturers and are specified for frequency ranges to 40, 65, or 100 GHz. They provide a higher density of connections that typical threaded SMA connectors. A long standing issue with these connectors is calibration. There are no or very limited calibration kits. This paper proposes a simple method to characterize these connectors over the full frequency range without a special calkit. Results will be compared to EM Simulation data for the connectors and adapters.
Presenter: O.J. Danzy is a RF and Microwave Application Engineer at Keysight Technologies specializing in areas surrounding physical layer test, network analysis, test system design and automation. Most recently he has focused on fixture removal and in-fixture calibration methods and techniques for multiport network analysis applications. He received Bachelor of Science in Electrical Engineering from Tennessee State University and a Master of Electrical Engineering from Cornell University.
Workshop 2: Signal Integrity Simulation Strategies for Accurate and Fast Results
Dr. Tracey Vincent
Application Engineer, CST
Abstract: The drive toward increased integration densities of electronic devices has led to smaller transmission line conductor sizes and structures consisting of multiple lossy dielectrics. At the same time, higher bit-rates of 100 GBits/s, has led to increased loss due to dispersive permittivity, skin-effects, and surface effects. To develop realistic simulated insertion loss results, all insertion loss components need to be considered and accounted for. Dielectric and conductor loss components require careful material parameterization and structure set up. The robustness of virtual prototyping strongly depends on the quality of the input parameters for EM simulation. Options for including plated materials influence and surface roughness contribution to conductor loss will be discussed. Dielectric loss modeling including the ability to determine/extrapolate dielectric loss will also be explored.
Presenter: Tracey is an Application Engineer with the CST of America team, Framingham, MA focusing on Signal Integrity and Materials Characterization for 3D simulations. She has a combined Bachelors/Masters Degree in Electrical and Electronic Engineering from Herriot-Watt University in Edinburgh, Scotland where she specialized in microwave theory and electromagnetics. She also completed a Masters degree in Electrical and Electronic Engineering at Napier University, Scotland UK, where she wrote an FEA program to solve fields in Ferrimagnetic materials. Tracey has previously been employed with Filtronic Comtek (UK), Aeroflex (UK) and Barry Industries (USA) where she gained experience in designing circulators, combiners, power amplifiers, transitions and filters. She completed her PhD at WPI in Worcester MA, USA in 2009, where she investigated the effect of material topography on RF signal loss.
Plenary Speaker 2: Bruce Archambeault, Ph.D.
Dr. Bruce Archambeault
IBM Distinguished Engineer Emeritus, IEEE Fellow
PCB Effects for Power Integrity
Abstract: Most of the noise on power planes can be directly traced to the I/O drivers in the ICs as they drive signals onto PCB traces. Decoupling capacitors are typically used to try and reduce this noise. The effectiveness of the decoupling capaitors depends on a number of issues and is usually limited by the inductance of various portions of the path between the decoupling capacitor and the IC. This talk will investigate the various portions individually, and identify how to optimize each portion for the best overall design.
Presenter: Dr. Bruce Archambeault is an IEEE Fellow, an IBM Distinguished Engineer Emeritus and an Adjunct Professor at Missouri University of Science and Technology. He received his B.S.E.E degree from the University of New Hampshire in 1977 and his M.S.E.E degree from Northeastern University in 1981. He received his Ph. D. from the University of New Hampshire in 1997. His doctoral research was in the area of computational electromagnetics applied to real-world EMC problems. He has taught numerous seminars on EMC and Signal Integrity across the USA and the world, including the past 12 years at Oxford University.
Dr. Archambeault has authored or co-authored a number of papers in computational electromagnetics, mostly applied to real-world EMC applications. He is a member of the Board of Directors for the IEEE EMC Society and a past Board of Directors member for the Applied Computational Electromagnetics Society (ACES). He currently serves as the Vice president for Conferences of the EMC Society. He has served as a past IEEE/EMCS Distinguished Lecturer , EMCS TAC Chair and Associate Editor for the IEEE Transactions on Electromagnetic Compatibility. He is the author of the book “PCB Design for Real-World EMI Control” and the lead author of the book titled “EMI/EMC Computational Modeling Handbook”.
Lunch Time Speaker, Priya Baskaran: Board Design Methodologies Used to Achieve Power, Performance, and Cost Balance in Mobile Devices
Staff Engineer, Qualcomm
Abstract: In mobile system and board design, there are various design considerations that are taken into account in order to achieve the perfect balance that will succeed in certain market tier. This presentation will go over some of the design solutions used to tackle some of the challenges. It will mainly focus on system architecture and board design techniques for voltage regulation, Power Distribution Network (PDN) design and signaling as well as signal integrity.
Presenter: Priya Baskaran has 8+ years of experience as a baseband hardware engineer and was involved in the design of various Qualcomm processor and Modem products. Priya is currently working as a hardware lead for one of the value tier Snapdragon platforms with responsibilities that encompass engineering, product test and verification. Priya holds a Bachelors from the University of Madras, India and a Masters from the Penn State University.
Plenary Speaker 3: Dr. Stefaan Sercu
Dr. Stefaan Sercu
Causality problems related to the numerical modeling of interconnects and connectors
Abstract: S–parameter models are widely used for simulating connectors and high speed interconnects. They include all high frequency effects (loss, skew, mode conversion, …) and S-parameters can easily be generated with a full wave solver or with a network analyzer. Due to the numerical representation of S-parameters (finite bandwidth and only known at discrete frequency points) causality problems can occur when time domain simulations are performed. In this presentation we will give an overview of the different problems that can occur and how they can be eliminated or minimized. A distinction will be made between problems caused by bandwidth limitation, frequency domain sampling and non-perfect model generation.
Presenter: Stefaan Sercu obtained a PhD degree in electrical engineering from the university of Ghent in 1999 and is currently a SAMTEC signal integrity engineer with more than 15 years experience in the connector industry. His work focusses on all SI aspects related to the modeling, simulation and characterization of high-speed connectors and interconnects.
Workshop 3: Automating the SI/PI Workflow
Abstract: As product release cycles become compressed due to customer demands, the need for electromagnetic analysis does not disappear. Instead, more pressure is placed on SI engineers to automate their workflow to churn through more simulations in less time. Recent updates to the ANSYS SI product suite accelerate this throughput by providing the full spectrum of interactivity within the design flow. Engineers can work within the graphical interfaces to inspect problem areas, or completely automate the extraction/analysis/reporting process.
Presenter: Tom MacDonald is a graduate of Worcester Polytechnic Institute with an M.S. in Electrical Engineer and a B.S. in Electrical & Computer Engineering and Physics. Before coming to ANSYS, Tom worked at Intel in IO design verification on Itanium and Xeon products while collaborating with the next-generation SERDES specification teams for next-generation serial communications.
Workshop 4: Working with IBIS-AMI Models
IC Design, Expert Technical Consultant, Keysight EEsof EDA