April 16, 2021
| Time | Events |
|---|---|
| 8:00-8:30 |
Registration & BreakfastZOOM |
| 8:30-9:30 |
Welcoming RemarksDr. John Mason Jr.
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| 9:40-1:00 |
Workshop 1:
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| 11:10-12:10 |
Plenary Speaker 2Title: How to Avoid Getting Totally SkewedBill Hargin, Director of Everything, Z-Zero Corporation Abstract: Everything that happens in the process of building a PCB works against signal quality. This is the underlying reason we spend so much time with “signal integrity”—the electrical world and the physical world are fighting against each other. As signaling speeds continue to double with Gen 5.0 SERDES interconnect standards, there’s no end in sight, and new methods of addressing high-speed issues are necessary to achieve both first-pass success and to have confidence that random variations in manufacturing or alternate PCB material sources won’t expose weaknesses in the planning process. Glass-Weave Skew (GWS) – also referred to as the Fiber-Weave Effect (FWE) – is one such issue that seems to be misunderstood on a pretty wide scale. Glass weave skew is an increasingly important problem above 10 Gbps. With typical differential skew rates between any pair of lines on the order of 2.5 psec/inch, it only takes an 8 inch long differential pair to accumulate a total line to line skew of 20 spec, which is the total skew budget in most designs. In this presentation, we will cover the causes of GWS as well as multiple possible solutions, with an eye toward cost and future-proofing your designs, preventing design and manufacturing teams from getting blind-sided by this issue. Bio: More than 10,000 engineers and PCB designers worldwide have taken Hargin’s workshop on high-speed PCB design, and Bill has spent much of the last 5 years focused on stackup, PDN design and PCB materials selection. With 25 years of experience dealing with PCB signal integrity, Mr. Hargin served as product manager for Mentor Graphics’ HyperLynx SI software. Bill worked for 5 years as the director of North American Marketing for Nan Ya Plastic’s PCB laminate division in Taiwan, is an associate editor for Printed Circuit Design & Fabrication, and is the founder of Z-zero—a manufacturer of software for PCB stackup planning, material selection and characterization. At DesignCon 2016, Mr. Hargin received the Best Paper Award for the Test and Measurement track, for a paper he coauthored on glass-weave skew.
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| 12:10-12:30 |
Lunch Break |
| 12:50-1:50 |
Lunch SpeakerTitle: Edge inference platform design for IoT/5G generation hardware with machine learning and artificial intelligenceMr. Chris Cheng, Distinguished Technologist in Primary Storage Division, Hewlett-Packard Enterprise Abstract: With the upcoming IoT/5G generation of hardware platforms, it is expected that most of the inference of data will be done at the edge or on prem at the customer sites instead of the current cloud based approach. With these high performance inference engines close to the hardware platforms, we can take advantage of their intelligence for our hardware reliability, system performance tuning and intelligent resource caching. Our presentation will be divided into three class of examples in edge inference applications. Big data, small learning example: These class of problems have typical feature size less than 100 and are mostly related to using sensor data to prediction future events. Typical application include proactive hardware failure prediction, security intrusion detection etc. Machine learning techniques can be used to proactively predict hardware (drives, cable etc. ) failures and remove them before they interrupt customer operations. Big data, medium learning example: Digital Twins or surrogate models with 100’s of features can be used to dynamically tune system performance. We will show an example of high speed SerDes surrogate model that can be used for automatic channel condition detection and performance tuning. Big data, deep learning example: Demand forecast in network and storage system will have very high dimension features (1000+) but will be very useful in tiering premium resources such as storage class memories for thousands of online customers if their demands can be predicted. Bio: Chris Cheng is a Distinguished Technologist in Primary Storage Division of Hewlett-Packard Enterprise. He is responsible for managing hardware machine learning development and high speed design within the Storage Division. He also held senior engineering positions in Sun Microsystems where he developed the original GTL system bus with Bill Gunning. He was a Principal Engineer in Intel where he led high speed processor bus design team. He was the first hardware engineer in 3PAR and guided their high speed design effort until it was acquired by Hewlett Packard.
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| 2:00-3:00 |
Plenary Speaker 3Title: Machine Learning Applications of SI/PIDr. Zhiping Yang and Dr. Tianjian Lu, Google corporation Abstract: Machine learning (ML) methods, particularly deep learning (DL), have recently transformed computer vision, speech recognition, and recommendation. The success is enabled by three main factors: innovative ML models and algorithms, massive amounts of data, and scalable software and hardware systems. It is tempting to ask whether ML and DL can also be useful to signal and power integrity, especially in the areas of modeling and simulation. Conceptually, it is plausible: given rich historic data, characterizing devices and systems maps to regression or classification in ML, whereas designing new devices and systems is amenable to generative models. In fact, the promise has been borne out by several recent attempts, which are presented as four case studies in this talk. Among the four case studies, two are related to power integrity including (1) the application of genetic algorithms and neural networks (NNs) in optimizing decoupling capacitor placement and (2) the impedance prediction of power distribution networks with NNs; and the other two are related to signal integrity including (1) the prediction of eye-diagram metrics through solving a regression problem with support vector machines and NNs and (2) the predictions on the circuit-level transient behaviors with recurrent neural networks. Bios: Tianjian Lu (S’13–M’17) received the B.E. degree from the National University of Singapore, Singapore, in 2010, and the M.S. and Ph.D. degrees from the University of Illinois at Urbana-Champaign, Champaign, IL, USA, in 2012 and 2016, respectively, all in electrical engineering. Since 2016, he has been a Hardware Engineer with Google, Mountain View, CA, USA. His researchinterests include multiphysics modeling and simulation, signal and power integrity, and machine learning. Dr. Lu was the recipient of the Best Student Paper Award (The First Place Winner) at the 31st International Review of Progress in ACES, Williamsburg, VA, USA, in 2015, the Best Student Paper Award at the IEEE Electrical Design of Advanced Packaging and Systems, Honolulu, HI, USA, in 2016, and the P.D. Coleman Outstanding Research Award by the Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, in 2016. Zhiping Yang (S’97–M’00–SM’04) received the B.S. and M.S. degrees from Tsinghua University, Beijing, China, in 1994 and 1997, respectively, and the Ph.D. degree from the University of Missouri- Rolla, Rolla, MO, USA, in 2000, all in electrical engineering. From 2000 to 2005, he worked for Cisco Systems, San Jose, CA, as a Technical Leader. From 2005 to 2006, he worked for Apple Computer, Cupertino, CA, as a Principal Engineer. From 2006 to 2012, he worked with Nuova Systems (which was acquired by Cisco in 2008) and Cisco Systems, San Jose, CA, as a Principal Engineer. From 012 to 2015, he worked with Apple, Cupertino, CA, as a Senior Manager. He is currently a Senior Hardware Manager with Google Consumer Hardware Group, Mountain View, CA, USA. He has published more than 40 research papers and 17 patents. His research and patents have been applied in Google Chromebook, Apple iPhone 5S/6/6S, Cisco UCS, Cisco Nexus 6 K/4 K/3 K, and Cisco Cat6K products. His research interests include signal integrity and power integrity methodology development for die/package/board codesign, high-speed optical |
| 3:05-4:20 |
Workshop 2Title: De-embeddingEric Oseassen, Rohde & Schwarz USA, Inc. and Jason Ellison, Amphenol LLC Bios: Eric Oseassen is an application engineer Rohde & Schwarz America. He holds a BSc from the City College of New York and an MSc from NYU Polytechnic. Eric has served in several roles, including R&D for the Aerospace community, Field Applications and Remote Sensing Development. Eric He is a plank-owner at two startup companies in the early aughts. His core interests include Amplifier and Converter Design & Characterization and Signal Integrity issues Jason Ellison received Master's of Science degree in electrical engineering from Penn State University, Harrisburg, PA, USA, in December 2017. He currently works as a Signal Integrity Engineer, developing high-speed interconnects, lab automation technology, and calibration technology at Amphenol. He founded Arcane Technologies LLC and writes technical publications for journals such as “The Signal Integrity Journal”. Mr. Ellison is a DesignCon technical program committee member.
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