Plenary Speaker 1: Brandon Gore
Signal Integrity Engineer, Intel Corporation's Packaging and Interconnects Group
"25Gbps and Beyond Ethernet Channel Specifications - Channel Operating Margin (COM)"
Abstract: During the development 100Gb/s Backplane and Copper Cable Ethernet by the IEEE P802.3bj Task Force, a new paradigm for channel qualification was introduced. No longer are electrical channel characteristics from device to device informative (recommended). The channel specifications are now normative and must meet a specified Channel Operating Margin (COM). COM is a signal to noise ratio in the context of a signaling architecture. The concept of a channel operating margin specification provides the unifying budget of the whole system, transmitter, receiver, and channel.
This talk will introduce COM concepts and contrast these with previous electrical channel masks. Design vectors that compete with signal integrity goals (best channels in the world!) and give rise to signal integrity challenges will be discussed.
Presenter: Brandon Gore is presently a signal integrity engineer within the Data Center Group at Intel Corp. developing platform level design guidelines for high speed differential signaling. His primary focus is high speed ENET interconnect guidelines. Brandon received his B.S.E.E. degree from Mississippi State University. He is currently a Doctoral Candidate at the University of South Carolina under Dr. Paul Huray where he also received a M.S.E.E. degree in Electrical Engineering.
Workshop 1: Signal Integrity Tips and Techniques Using TDR-VNA Modeling
OJ Danzy and Russ Kramer, Keysight Technologies
"Signal Integrity Tips and Techniques Using TDR-VNA Modeling"
Workshop 2: Advanced SI Analysis – Layout Driven Assembly
Application Engineer, ANSYS
Abstract: As the voracious appetite for technology continually grows, so too does the need for fast turn around times and efficient techniques for characterization. To improve timeliness of returns, ANSYS SI product suite offers new functionality to enhance the user experience with layout driven assembly. By combining HFSS for connectors and HFSS 3D Layout for boards, this methodology allows us to apply current best solving techniques to our problems for optimal turnaround time and accuracy.
Presenter: Tom MacDonald is an Application Engineer for ANSYS specializing in the support of Signal and Power Integrity customers. Prior to joining ANSYS, he graduated from Worcester Polytechnic Institute with an M.S. in Electrical Engineering and a B.S. in Electrical & Computer Engineering and Physics. He also worked at Intel in IO design verification on Itanium and Xeon products while collaborating with the next-generation SERDES specification teams for next-generation serial communications.
Plenary Speaker 2: Alfred Neves
Chief Technology Officer, Wild River Technologies
"RF Old School Microwave Structures and Their Application for Modern Signal Integrity"
Lunch Time Speaker: Dr. Eric Bogatin
Dean, Lecroy/Teledyne Systems Integrity Academy
Author of the hugely successful book, Signal and Power Integrity Simplified
"Forensic Analysis of Closed Eyes- How do you Debug a High Speed Serial Link"
Plenary Speaker 3: John D'Ambrosia
Senior Principal Engineer, NA IP Standards Team, Futurewei, a subsidiary of Huawei
Chair, IEEE P802.3bs 400GbE Task Force
"The Ethernet Rate Explosion"
Abstract: Over the past three years, Ethernet has undergone an explosion of innovation, as it adds new specifications to support operation from DC to 400Gb/s. This portfolio consists of solutions ranging from operation over copper traces for a few millimeters to optical fibers that range up to 40 km. The underlying signaling technologies have moved beyond 25 Gb/s to 50 Gb/s, and we are now looking at a world that will employ PAM4 modulation. This will impact system designers and signal integrity engineers, as they consider the selection of connectors, board materials, components, cabling, and other parts. However, these fundamental signaling technologies are being leveraged over a host of Ethernet rates, allowing engineers to address a host of solutions targeting computing and networking applications.
Workshop 3: Modeling Complex Structures in Electromagnetics Using a Hybrid Algorithm
Signal Integrity Engineer, FCI
Abstract: Modeling complex electromagnetic structures using conventional numerical electromagnetic tools is extremely challenging due to the fact that these structures are multi-scale in nature. The multi-scale nature of these problems exacts a huge computational cost when solved using conventional numerical electromagnetic techniques - both in terms of memory and time. In this presentation, a novel hybrid algorithm is introduced which handles such problems efficiently as well as accurately.
Presenter: Kapil Sharma is a PhD candidate in the Electrical Engineering department at Penn State University. He is also working as a SI R&D co-op Engineer at Amphenol FCI-USA where he supports development of new products and performs EMI analysis of high-speed interconnects. His research interests are numerical electromagnetics, EMI/EMC analysis, signal integrity, and microwave engineering.
Workshop 4: 28 GBaud PAM4 Characterization in Preparation for 400G
Product Specialist, Tektronix
Abstract: 28GBaud PAM4 signal characterization in preparation for emerging 400G CDAUI8 and OIF-CEI-56G standards. Higher order levels of signal modulation present unique challenges for signal acquisition, clock recovery and signal equalization. This track will present methods to advance analysis capabilities vital for the upcoming speed shift to 400G.
Presenter: John Smith is a Product Specialist at Tektronix, specializing in high speed signal integrity measurements. He holds a MSEE from Lehigh University in Optical Communications and BSEE from Washington University. John has over 15 years experience in the test & measurement industry.
Presentation PDFs will be added to the following archive as they are made available to the Conference organizers.