April 28, 2023
| Time | Activity |
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8:00 - 8:30 |
Registration |
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8:30 - 9:30 |
Welcoming Remarks Title: “Managing Differential Via Crosstalk and Return Via Placement” Abstract: Crosstalk between differential vias is becoming an increasingly important impairment for the latest generations of high-speed serial channels. While differential vias may be able to control reflections over the required bandwidth, they may not be able to provide the required crosstalk isolation. Using measured data to 67GHz and eigenmode based electromagnetic modeling, this talk will indicate clearly the crosstalk coupling to be expected and provide an engineering model of the design parameters that affect that coupling. The crosstalk coupling is determined by the radial TEM waves generated by the signal vias, combined with those reflected from the return vias. Standing waves between arrays of return vias can form resonant cavities, and these resonant cavities play a particularly important role in determining the crosstalk coupling as a function of frequency. A common configuration is a rectangular array of return vias surrounding a differential via pair. This configuration has both a single ended and a differential resonant mode, and two differential pairs within a rectangular grid of return vias form a two-section microwave filter that is a crosstalk coupling path between the two differential pairs. For a 1mm via grid spacing, the passband occurs slightly above 60GHz, making the out of band rejection (crosstalk loss) quite high below 20GHz and acceptable up to 40GHz, but entirely unacceptable above 40GHz. Other return via configurations have different frequency responses, and they will be presented as well. Bio: Michael Steinberger, Ph.D. is a Consultant Software Engineer at MathWorks and has over 30 years of experience designing very high-speed electronic circuits. Dr. Steinberger holds a Ph.D. from the University of Southern California and has been awarded 14 patents. He was DesignCon 2015’s Engineer of the Year. He is currently responsible for the behavioral modeling of mixed analog and digital circuits. Before joining MathWorks, Dr. Steinberger was the lead architect for high-speed serial channel analysis at SiSoft. |
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9:40 - 11:10 |
Workshop 1, Main room Title: "Intuitive Simulation and Measurement Workflow for Hardware Engineers" What the audience will learn or target audience: New hardware engineers will learn how to fix three common cases of signal integrity problems. Experienced hardware engineers will have a good refresher on their signal integrity basics. Both will learn to create an optimized simulation and measurement design cycle within their team. Abstract: Hardware engineers often encounter the performance verification bottleneck. The bottleneck occurs at the final step of every printed circuit board (PCB) design. If there is no simulation and measurement workflow to quickly validate designs and identify signal integrity (SI) issues before the final verification, you are not maximizing your team’s productivity. This presentation demonstrates an intuitive simulation and measurement workflow to maximize your PCB design productivity. Three case studies of PCIe channel will provide fixes to common signal integrity problems. The problems addressed are related to controlled impedance, return loss and insertion loss. The presentation closes with multi-domain analysis on an example PCIe channel. Analyses such as mixed-mode S-parameters, eye diagram, time domain reflectometry (TDR) are crucial in troubleshooting SI issues. If you are new to signal integrity, this session will give you a head start on your signal integrity journey. For experienced hardware engineers, this presentation is an excellent refresher on the fundamental SI analyses and concepts in both simulation and measurement. Workshop 2 Title: "Connector and Cable Assembly Challenges for PCle 5.0 and 6.0" Demos by Eric Oseassen - R&S Applications Engineer Abstract: PCIe 4.0 has become mainstream with not only in typical motherboard applications, but also in some niche applications link NVME2.0. This protocol runs at 16 Gb/s with NRZ modulation. PCIe is now working to release generation 5 and 6 protocols. They operate at 32 Gb/s NRZ and 64Gb/s PAM-4 respectively. The higher datarate means higher bandwidth needs from the interconnect. We’ll present the requirements for PCIe interconnects in detail, give examples of hardware that meets these requirements, and show hardware and software needed to characterize this hardware both for qualification and production. Examples of this hardware and measurement equipment will also be shown at live at the Symposium. Bio: Jason Ellison graduated with a Master of Science from Penn State Harrisburg in 2017 and is the Principal Signal Integrity Technologist at Rohde and Schwarz. He was a technical editor of the IEEE 370 specification, created and published the IEEE open-source de-embedding algorithm, has several IEEE publications, and holds many patents related to high-speed connector design. Demo 1: Power Integrity Demo - R&S RTP16 showing a BODE plot of SAMTEC power cable assembly. Demo 2: ZNBT40 demonstrating the capability of measuring four differential pairs of a high speed cable assembly simultaneously. All demos run by Eric Oseassen - R&S Applications Engineer AcceleRate® HP Si Evaluation Kit - SI test platform for evaluating 0.635 mm pitch, 112 Gbps PAM4 AcceleRate® HP high-performance arrays. Samtec 0.635 mm pitch, 112 Gbps PAM4 AcceleRate® HP high-performance arrays support high-performance applications with maximum routing and grounding flexibility via an open-pin-field design. The AcceleRate® HP SI Evaluation Kit provides system designers and SI engineers an easy-to-use solution for testing AcceleRate® HP connectors. The AcceleRate® HP SI Evaluation Kit delivers a high-quality system with robust mechanical design. |
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11:15 - 12:15 |
Plenary Speaker 2 Title: “Stackups: The Design Within the Design” Description: This workshop will guide design teams through the process of evaluating and selecting the right laminate for a design, creating PCB stackups that meet the requirements of complex, multilayer boards that work right the first time, within budget, and with reproducible results across multiple fabricators. The course will go into detail on tradeoffs between loss and cost, including dielectric loss, resistive loss, surface roughness, as well as glass-weave skew. After attending this course, students will be knowledgeable of PCB laminate tradeoffs, the laminate-materials market, and the process of troubleshooting problematic stackup designs. Attendees will also be exposed to cost-effective strategies for controlling loss and glass-weave skew and will receive a free digital or print copy of Bill's iConnect007 book, "Stackups: The Design Within the Design." Bio: Bill Hargin is the chief everything officer at Z-zero, developer of the PCB stackup design and material selection software, Z-planner Enterprise. Bill is an industry pioneer, with more than 25 years working in PCB signal integrity and manufacturing, while authoring dozens of articles on signal integrity, stackup design, and material selection. Hargin is also the author of the iConnect007 publication “Stackups, the Design within the Design,” a regular columnist for Printed Circuit Design and Fabrication magazine, and a contributing author for the Printed Circuits Handbook. Bill is a regular speaker and panelist at both DesignCon and PCB West, and more than 10,000 engineers and PCB designers worldwide have taken his workshop on high-speed PCB design. Mr. Hargin served as director of marketing for Mentor Graphics’ HyperLynx SI software and as the Director of North American Marketing for Nan Ya Plastic’s PCB laminate division in Taiwan before founding Z-zero. |
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12:45 - 1:45 |
Plenary Speaker 3 Title: “Developing High-Quality Test Fixtures for De-embedding of S-Parameters” Abstract: Extracting high-quality S-parameters for a DUT from measurements inherently involves de-embedding them from a total structure that includes test fixture lead-ins and lead-outs. These lead-ins/outs typically include probes or connectors, and potentially some length of non-coaxial transmission-line, e.g., stripline or microstrip on a PCB, as well as via transitions, in addition to the DUT. A common de-embedding approach often used for DUTs on printed circuit boards, packages, and cabling for example, utilizes a 2X Thru, or 1X Open together with the total structure to extract the DUT S-parameters. For many current high-speed and high-frequency applications, it is necessary to do 3D full-wave electromagnetic simulation in order to develop a high-quality test fixture from which successful de-embedding can result. The features that comprise good lead-in/out test fixturing from which DUT S-parameters can be extracted will be detailed in this presentation. EM simulation for developing test fixtures will be discussed and examples provided. This presentation will also briefly discuss making quality S-parameter measurements with a VNA and provide comparison results. Examples for de-embedding to 50 GHz will be presented. Bio: Dr. Jim Drewniak is the Curator’s Professor Emeritus, Missouri S&T, EMC Laboratory, and President of Clear Signal Solutions, [email protected] |
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1:45 - 2:45 |
Plenary Speaker 4 Title: “VRM Modeling and Stability Analysis for the Power Integrity Engineer” Abstract: In the world of power electronics, the focus is on the power supply, and the load is modeled as a simple resistor. In the world of power integrity, the focus is on the decoupling capacitors required for the digital load, and the power supply is modeled as a simple resistor in series with an inductor. In the real world, neither assumption solves the problem of simulating the power delivery ecosystem with switching power supply control loops, gigabit switching digital loads, and a PCB network of filtering and decoupling components. The challenge is how to simulate the Power Integrity ecosystem and include the feedback loop and switching noise of a switch mode power supply (SMPS) without waiting days for the simulation results. The solution presented here uses control loop theory state space equations to create a behavioral model of an SMPS that allows for fast simulation. This Sandler State Space Average Model previously published [1] has the fidelity to include the dynamic control loop behavior for stability assessment, large signal and small signal noise ripple, and power supply rejection ratio. The model also works with the Non-Invasive Stability Measurement method to assess the control loop phase margin from simple output impedance data. Bio: Benjamin Dannan is a technical fellow and an experienced signal and power integrity (SI/PI) design engineer, advancing high-performance ASIC and FPGA designs at Northrop Grumman. He is a Keysight ADS Certified Expert with expert-level proficiency in high-speed simulation solutions and multiple 3D EM solutions. He has expert-level proficiency with multiple test and measurement solutions, including oscilloscopes, vector network analyzers (VNA), Time Domain Reflectometers (TDRs), function generators, and EMC lab testing equipment. Dannan is a senior member of IEEE, as well as a DesignCon TPC member with a multi-faceted background that includes a wide range of professional engineering and military experiences. His multiple years of engineering experience include designing, developing, and launching production products, ranging from ASICs, radars, fully autonomous robotic platforms, pan-tilt-zoom (PTZ) camera video systems, and ground combat vehicles. He is a specialist in signal and power integrity concepts, high-speed circuits, and multi-layered PCB design, as well as multiple years of experience with EMC product development and certifications to support global product launches. Additionally, he has extensive experience with Chip-Package-PCB-VRM power delivery network (PDN) principles. Benjamin holds a certification in cybersecurity, has a BSEE from Purdue University, a Master of Engineering in Electrical Engineering from The Pennsylvania State University, and graduated from the USAF Undergraduate Combat Systems Officer training school with an aeronautical rating. Benjamin is a trained Electronic Warfare Officer in the USAF with deployments on the EC-130J Commando Solo in Afghanistan and Iraq totaling 47 combat missions, as well as a trained USAF Cyber Operations Officer. In addition, he has co-authored multiple peer-reviewed journal publications. He has received the prestigious DesignCon 2020 best paper award, given to authors leading as practitioners in semiconductor and electronic design. |
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2:50 - 4:20 |
Workshop 3 Main Room Title: "Leveraging Automation to Optimize Assemblies using Encrypted 3D Components" Abstract: One of the biggest challenges for any Signal Integrity analysis is to get models from vendors (such as connectors, cables, antennas), tech files for 3D IC, and 3D components in general to assemble the entire serial channel. Concatenating S-parameters is a valid approach, but with today’s high-speed protocols the coupling and interaction between PCB and 3D components are extremely important and must be considered. In this Workshop we will see how Ansys HFSS can be used to assemble complex ECAD+MCAD models using Encrypted 3D Components in an automated way using pyAEDT, and how users can optimize entire serial channels using several numerical techniques. In this workshop we will be presenting:
Bio: Juliano Mologni is the SI/PI Lead Product Manager at Ansys. Over 20 years of experience in computational electromagnetics, author of more than 60 peer reviewed journal and conference papers and patents related to automotive EMC. Holds a BSc degree in Electrical Engineering, a MSc degree in Microelectronics and his PhD thesis involves research on Automotive EMC and Signal Integrity. Workshop 4 In this Workshop you will see how Cadence design and analysis tools have leveraged the development of SerDes IP by the Cadence PHY IP team to ensure that simulation technology is ready for the mainstream that will adopt use of these very popular high-speed interfaces. Included in the Workshop will be:
Bio: Jared James is a Senior Principal Product Engineer for Cadence Design Systems focusing on serial link and PDN analysis. During his 20 years at Cadence, he has held various roles as an analog/mixed signal circuit designer, a SERDES test engineer, followed by a product engineering position supporting multiple SERDES IP. He is currently the product engineer for the SystemSI serial link tool, the SystemPI power analysis tool and the AMI Builder modeling tool. |