17th Central PA Signal Integrity Symposium and MASH Forum
April 19, 2024
Save the date for this year's symposium
and Mid Atlantic Semiconductor Hub (MASH) Forum.
Preliminary Program
| Time | Events |
|---|---|
| 8:00-8:30 | Registration and Breakfast |
| 8:30-9:30 |
Welcoming Remarks: Dr. David Callejo Pérez, Interim Chancellor and Dean, Penn State Harrisburg Plenary Speaker 1, Capital Union Building (CUB), Convocation Room Title: Global Semiconductor Future Trends Abstract: Dr. Coughlin will be discussing the CHIPS act and the implications of it for the semiconductor industry and its associated influence on the connector industry and consumer electronics |
| 9:40-10:40 |
Workshop 1 CUB Convocation Room Title: Navigating Signal Integrity Challenges: From traditional PCBs to Chiplets Abstract: This two-part presentation addresses two aspects of modern signal integrity challenges: printed circuit board (PCB) designs and chiplet-based designs. The first segment delves into the impact of fabrication processes on the signal integrity performance of PCBs. Through an exploration of parameters such as trace etch-back, and substrate height, coupled with an analysis of cross-sectional geometry, participants gain a theoretical understanding of material properties' impact on signal integrity metrics. Workshop 2, EAB 110 Title: Charting the Path to Excellence: Promoting a World-Class Workforce in the Semiconductor Industry Abstract: Through this presentation, participants will learn about a workforce development strategy the Mid-Atlantic Semiconductor Hub (MASH) will utilize to promote excellence in semiconductor manufacturing within the U.S. An emphasis of this session will be placed on comprehending the workforce development needs of the industry and promoting the transfer of education through advanced learning and skill development opportunities. |
| 10:45- 11:45 |
Plenary Speaker 2, CUB Title: The Mid-Atlantic Semiconductor Hub (MASH) Abstract: A distributed network of resources and talent to reassert U.S. leadership in semiconductor manufacturing. |
| 11:45-12:15 | LUNCH |
| 12:15-1:15 |
Plenary Speaker 3 . CUB Title: Low-Cost SI Solutions for Every Engineer Abstract: A general law of nature seems to be that things of higher value cost more. However, there are a few solutions that are surprisingly high value that do not cost very much. These solutions offer a unique opportunity to enable a useful solution on a personal budget. I will show three software and two hardware solutions that are either free or under $5. You will see a free animation tool useful for visualizing reflections of signals in TDR applications. You will see why near and far end cross talk have a very different signature. You will see how anyone can view any S-parameter file in the frequency domain or in the time domain in single-ended or differential form. Then you will see how to make a 15 GHz bandwidth launch with a $0.35 SMA connector. Finally, I will show you how you can make a 5 Gbps PRBS signal for $5. |
| 1:20-2:20 |
Plenary Speaker 4, CUB Title: ISI across HVM beyond 32G Abstract: In this presentation, we discuss the challenges of ISI across the manufacturing space and highlights it as one of the major contributors to degradation of link performance and system reliability for data rates beyond 32G. Quantifying the impact and yield of a system requires engineers to accurately quantify the impact of ISI from the multiple manufacturing tolerances of the system components, to do this all-manufacturing corners must be considered. This presents its own challenge, where the solution space scales exponentially in size, and resolving the entire manufacturing corner space becomes impractical. In order to successfully predict performance of the system across manufacturing, we highlight the importance of developing robust workflows that employ linear time invariant systems whose solution spaces can be extrapolated with appropriate statistical fitting. |
| 2:25-3:25 |
Plenary Speaker 5 Title: The Journey to 1.6 TbE Abstract: TBA |
| 3:30-4:30 |
Workshop 3 (CUB) Title: A novel VNA based utility to create “N” port S-parameter matrixes with “M” physical ports, applied to arbitrary topologies; where M<N Abstract: We will demonstrate a novel utility that allows operators to build a multiport S parameter matrix using a fixed number of VNA physical ports. This approach is independent of topology, supporting single ended, balanced, and other mixed-mode variations, which allows operators to define a physical port combination. Additionally, test plans for mixed mode port combinations can be readily implemented. A firmware utility guides the operator on implementing physical connections. Correlation pf measured S parameters and modeled performance will be highlighted, demonstrating how advanced de-embedding facilitates correlation. Workshop 4 EAB 110 Title: Signal Integrity Applications in Intelligent Connectivity Systems Abstract: Modern communication systems shuffle data through a vast network of devices that are extremely complex. Applications such as next generation Software Defined Vehicles, Smart Cities, Industrial Internet of Things, and more all communicate via intelligent network systems consisting of devices ranging from the size of semiconductor chips all the way to satellite networks. The path data takes from the complex processing in a datacenter die all the way to the end user can vary between hard linked electrical cables and wireless links running 10’s of Mbps to 10’s of Gpbs to fiber optic links pushing Tbps. These paths, from chips to chips inside complex packages, or from chips to PCBs to connectors to cables inside datacenters, or from Datacenters and Edge systems to end users via wireless connections, all require an increased sensitivity to signal and power integrity. This presentation will discuss these various communication paths and some advanced methodologies that can be used to better characterize these systems. |