Annual Symposium

Welcoming Remarks

Plenary Speaker 1, Capital Union Building (CUB), Convocation Room 
Designing Vertical Signal Transitions in Next-Generation High-Speed Data Channels
Dr. Bill Kim, Missouri Science and Technology University

Abstract
Vertical interconnects, commonly referred to as plated through-hole (PTH) vias represent a critical design constraint in both signal integrity and power integrity of PCBs. Consequently, optimizing these interconnect components is imperative for high-speed channel design, particularly for data rates such as PCIe Gen7, which can reach up to 128 Gbps. Traditionally, a 3D finite element method (FEM) solver is employed for via optimization; however, this requires substantial computational resources. In response, a mode-decomposition-based equivalent via (MEV) model was introduced to predict the electrical performance of vias and demonstrates accuracy up to frequencies of 50-60 GHz. Furthermore, a high-speed via model that considers anti-pad inductance, supported by a comprehensive physical understanding of the via, is proposed. This model includes a closed-form formula for inductance, enabling the prediction of insertion loss and return loss for frequencies up to 150 GHz for any specified via parameters. Additionally, the model has been extended to account for differential vias with single-ended anti-pads by incorporating via-to-via coupling. This high-speed via model has been validated against full-wave simulations, exhibiting an error of less than 2 dB up to 150 GHz. Beyond via modeling, this talk explores additional strategies to enhance the performance and longevity of copper-based vertical interconnections in high-speed digital PCBs.
Bio
Dr. DongHyun (Bill) Kim is an Assistant Professor of Electrical and Computer Engineering and a College of Engineering and Computing Dean’s Scholar at the Missouri University of Science and Technology in Rolla, MO, USA. He is also a faculty member at the Center for Electromagnetic Compatibility, a National Science Foundation Industry/University Cooperative Research Center. His current research interests encompass nanometer-scale devices, through-silicon via (TSV) technology, dielectric material characterization, signal integrity (SI), power integrity (PI), temperature integrity (TI), electromagnetic compatibility (EMC), and electrostatic discharge (ESD) in high-speed digital channels.
 

Workshop 1, CUB Convocation room
Your Pathway to PCI Express 6.0 
Neil Hoffman, Keysight

Abstract
PCI Express 6 is a revolutionary step with challenges never seen before: a move from NRZ to PAM4 with eye height of only 6mV. Bit errors are handled with forward error correction (FEC); new measurements are required like 6JU and SNDR. Keysight is a major contributor to the PCI-SIG primary working groups and has been since their inception. Keysight helps you navigate through these complex requirements with unmatched expertise and world-leading support. You need a smooth transition from PCI Express® 5.0 to 6.0 where the integrity of your PCIe measurements are backed by leading-edge tools.

Bio
Neil Hoffman is a Digital and Optical Solutions Specialist for Keysight Technologies. He is a 35 year veteran of the test and measurement industry, holding various positions during that time. For the last 20 years, he has focused on digital, analog and optical applications involving scopes, BERT’s, AWG’s, logic analyzers and optical test and measurement equipment.
 

Workshop 2, Educational Activities Building (EAB), 101
Preparing for PCIe Electrical Measurements Beyond 64 GT/s
Rohde & Schwarz Eric Oseassen

Abstract
Preparing for PCIe 7.0: Understanding measurement path challenges and how to interface instrumentation to 65 GHz chips, thus requiring 67 GHz Vector Network Analyzers.

Bio
Sr. Staff Application Engineer; Rohde & Schwarz USA
Eric holds an MSc in RF Theory & Techniques from Polytechnic Institute of New York University and a BEEE from City University of NY
He has over two decades of experience, spanning Design, Test, and Fabrication in the areas of SATCOM, Mil-Aero and Signal Integrity

Plenary Speaker 2, Capital Union Building (CUB)
448G per Lane Signal Integrity Challenges & Design Considerations
Mr. Howard Heck, System Architect at TE Connectivity

Abstract
This presentation discusses the signal integrity related challenges that the industry faces as we scale pluggable I/O interfaces to 448G. We will begin by outline desired electrical characteristics (insertion loss, reflections crosstalk) for passive channels.  We then describe the ways in which physical structures and manufacturing consider may limit the scalability of existing channel component and discuss the implications on the choice of modulation scheme for 448G operation. The limitations suggest that new approaches are needed, and we will describe one such approach that can provide an optimized solution that overcomes the challenges that exist with existing channel structures.

Bio
Howard Heck is a System Architect at TE Connectivity, where he drives standards and technical solutions for high-speed signaling links for networking and AI applications. Throughout his career, his focus has been centered on signaling integrity, most recently on PAM4-based Ethernet solutions, where he has been a technical editor for multiple generations of the standard. Prior to the Ethernet role, he drove development of specifications and product solutions for Universal Serial Bus 3.0/3.1/3.2, spanning from initial spec development to post-silicon validation. He co-authored “Advanced Signal Integrity for High-Speed digital Designs”, a graduate level textbook on signal integrity, and from 1998 through 2009 taught signal integrity at the Oregon Graduate Institute. He was the chair for the IEEE Oregon joint CPMTCAS chapter from 2008 through 2023, and holds 44 patents
 

Plenary Speaker 3, Capital Union Building (CUB)
“Black Art” Elements of Extreme Signal Integrity
Al Neves, CTO Wild Rivers Technologies

Abstract
The signal integrity crisis in the 1990s was a major challenge in the electronics and telecommunications industries, specifically related to the design of high-speed digital circuits and systems. As electronic devices, particularly computers, began operating at higher frequencies and with more complex circuits, engineers faced significant problems with signal integrity (SI). This raised awareness around SI, which was further fueled by Howard Johnson and Martin Graham’s book on the topic, notably subtitled "A Handbook of Black Magic". Since then, we've faced increasingly complex challenges, unimaginable at the book’s publication time. However, significant progress has been made in Electronics Design (EDA), including methodologies, understandings of pcb high-speed design of vias and breakouts, skew impact, crosstalk, jitter analysis, and more. Additionally, IEEE P370 compliance specifications have been developed to help define SI metrics. Certainly, “Black Magic” represents compelling story telling and marketing (it sells books and SI services), but as we exceed 90GHz bandwidth and 224G signaling one must ask: are there still elements of the “Black Art” in SI?

Bio
Alfred P. Neves is the Founder and Chief Technology Officer at Wild River Technology. Al has 43 years of experience in the design and application development of semiconductor products, capital equipment design focused on jitter and signal integrity analysis and has successfully been involved with numerous business developments and startup activity for the last 29 years. Al focuses on measure-based model development, ultra-high signal integrity serial link characterization test fixtures, high-speed test fixture design, and platforms for material identification and improving measurement-simulation to 110GHz
 

Plenary Speaker 4, Capital Union Building (CUB)
Analyzing Large Signal Phenomena and Crosstalk in Time and Frequency Domain and Avoiding Ground Loop Effects 
Ben Dannan, Founder and Chief Technologist, Signal Edge Solutions

Abstract
As electronic designs evolve, managing power fluctuations becomes increasingly challenging due to lower voltage levels and tighter component tolerances. With rising data rates, shrinking supply voltages, and higher integration densities, issues such as jitter, noise, frequency-dependent loss, reflections, and crosstalk are more common than ever. These factors can significantly affect power rails, resulting in voltage sag and ground bounce. Power rail disturbances, in return, have an increasing effect on signal integrity, particularly through power supply-induced jitter and amplitude noise. Thus, analyzing power integrity and the performance of the power delivery network (PDN) on a printed circuit board (PCB) is now an essential part of the digital design process. 
In this session, you will learn more about:

• Analyzing large and small signal phenomena and the corresponding way of testing them
• Measuring PDN Crosstalk in the time and frequency domain
• Ground loop effects and how to avoid them

Bio
Benjamin Dannan is the Founder and Chief Technologist at Signal Edge Solutions. Benjamin Dannan is an experienced signal and power integrity (SI/PI) design consultant developing advanced packaging solutions for high-performance ASICs, chiplets, and complex FPGA designs. He is a Keysight ADS Certified Expert with expert-level proficiency in high-speed simulation solutions and multiple 3D EM solutions. He has expert-level proficiency with multiple test and measurement solutions, including oscilloscopes, vector network analyzers (VNA), Time Domain Reflectometers (TDRs), function generators, and EMC lab testing equipment.
He is a senior member of IEEE with a multi-faceted background that includes a wide range of professional engineering and military experiences. His engineering experience includes designing, developing, and launching production products, including ASICs, radars, fully autonomous robotic platforms, pan-tilt-zoom (PTZ) camera video systems, and ground combat vehicles.

He is a specialist in signal and power integrity concepts, high-speed circuits, and multi-layered PCB design, as well as has multiple years of experience with EMC product development and certifications to support global product launches. Additionally, he has extensive experience with Chip-Package-PCB-VRM power delivery network (PDN) principles.
His depth of expertise includes modeling large SoC designs, multi-chip modules (MCMs), and chiplets with frequencies in excess of multiple GHz using innovative technologies. He has multiple years of experience leading multiple products through EMC/EMI compliance testing activities for global market sales, including CE, FCC, IEC, CISPR, and other regulations. In addition to his experience and knowledge solving EMC non-compliance issues.

Benjamin holds a certification in cybersecurity, has a BSEE from Purdue University, a Master of Engineering in Electrical Engineering from The Pennsylvania State University, and graduated from the USAF Undergraduate Combat Systems Officer training school with an aeronautical rating. Benjamin is a trained Electronic Warfare Officer in the USAF with deployments on the EC-130J Commando Solo in Afghanistan and Iraq, totaling 47 combat missions, and a trained USAF Cyber Operations Officer. In addition, he was awarded the DesignCon 2025 Engineer of the Year, has co-authored multiple peer-reviewed journal publications, and has twice received the prestigious DesignCon Best Paper award, given to authors who are leading practitioners in semiconductor and electronic design.


 

Plenary Speaker 5, Capital Union Building (CUB)
SerDes IBIS-AMI Modeling and Signal Integrity Simulations with Genetic Algorithms. 
Mr. Andy Zambell, Senior Product Manager Marketing, MathWorks

Abstract
In high-speed digital communication, optimizing SerDes (Serializer/Deserializer) systems is crucial for maintaining robust signal integrity. This talk explores the application of genetic algorithms to enhance SerDes IBIS-AMI (I/O Buffer Information Specification - Algorithmic Modeling Interface) models and simulations. By using a genetic algorithm, we can achieve faster optimization of equalization settings without having to sacrifice accuracy. We also discuss the acceleration of signal integrity simulations, particularly in optimizing DDR5 write transfers, showcasing the potential of genetic algorithms in advancing high-speed digital communication systems.

Bio
Andrew Zambell received his B.S. in Physics from Lebanon Valley College in 2002 and his M.E. in Electrical Engineering from Penn State University 2022. He is currently a Sr. Product Marketing Engineer whose focus is on Signal Integrity, SerDes, and Mixed-Signal applications at MathWorks. Prior to joining MathWorks, Andy was a Signal Integrity Engineer at FCI USA LLC and Amphenol for a decade where he specialized in the new product development and customer support of high-speed backplane connectors. He also was involved in the development of industry standards such as SAS-3, IEEE 802.3bj, IEEE 802.3bs, IEEE 802.3by as well as several Optical Internetworking Forum Common Electrical I/O standards. Andy was also a high school physics teacher for three years and is a current member of the Institute of Electrical and Electronics Engineers.

 

Workshop 3, Capital Union Building (CUB)
Design and Considerations for Immersion Cooling Application
Mr. Stephen Smith, Senior Staff Signal Integrity Engineer, Amphenol

Workshop 4, Educational Activities Building (EAB), 110

TBD