2022 Symposium Program

April 29, 2022

Time Events
8:00 - 8:30


8:30 - 9:30

Welcoming Remarks

Welcome and Plenary Speaker 1, Main Room

Design and Modelling of Nonuniform Microstrip Lines for Tab-Routing Applications

Dr. Guoan Wang, Associate Professor, University of South Carolina

Abstract: Crosstalk has already become one of the dominant limiting factors for achieving higher data transfer rate. To reduce far-end crosstalk (FEXT), tab-routing is recently proposed for crosstalk mitigation to improve double data rate (DDR) channel performance. However, how to optimize the tabbed routing structures efficiently and accurately remains a question. This talk first presents equation-based solutions to coupled, asymmetrical, lossy, and nonuniform microstrip Lines for tab-routing applications. Analytical equation-based solutions are directly derived from the physical parameters of microstrip lines with interdigital trapezoidal tabs incorporated, resulting in their corresponding scattering parameters. Capacitance and inductance matrices under a quasi-static condition are derived from the cross-sectional dimensions of asymmetrical coupled microstrip lines with unequal widths. The frequency-dependent resistance–inductance–conductance–capacitance model is then converted, allowing complete equation-based solutions to their four-port Z-matrix, S-matrix, and ABCD-matrix. As an application example of tackling the complexity of transmission lines, the derived analytical method is applied to a transitional structure with linearly varying trace width in tabbed microstrip lines by the method of segmentation. In addition, a new concept of tab coupling fringing capacitance is specifically introduced to compensate for underestimated mutual capacitance at tab positions, which will improve the accuracy of the proposed approach. Numerical modeling results from commercial simulation tools are compared for validation purposes. As a conclusion, the proposed method and its versatility are demonstrated with applications to practical high-speed and high-density printed circuit board designs, which renders itself effective and efficient in an optimization process. Finally, methods of developing tabbed-routing structures with the integration of ferromagnetic and ferroelectric thin films for the improved signal integrity with reduced FEXT is presented.

Speaker Bios: Dr. Guoan Wang received his Ph.D. in Electrical and Computer Engineering from the Georgia Institute of Technology in 2006. He joined the Department of Electrical Engineering at the University of South Carolina in 2011. He was an Advisory Scientist responsible for on chip mmwave passives and wafer level RF MEMS technologies in IBM Semiconductor Research and Development Center from 2006-2011. His current research areas include tunable RF and microwave electronics, novel materials/techniques for smart RF applications, MEMS/NEMS, sensors and sensing systems, wireless energy harvesting, and 3D integrated devices/system. Dr. Wang’s research work has produced over 120 papers in peer-reviewed journals and conferences proceedings, one book (Smart RF Passive Components: Novel Materials, Techniques, and Applications, Artech House). He also has 51 granted patents and 50 pending patent applications.  

Dr. Wang is an Associate Editor for International Journal of RF and Microwave Computer-Aided Engineering and served as an Associate Editor of IEEE Microwave and Wireless Components Letters from 2013-2019, and guest editor for IEEE Access. He is vice-chair of Technical Coordinating Committee for IEEE MTT-13 Microwave Control Techniques, and member of MTT-6 RF MEMS and Microwave Acoustics. He has been served in Steering Committee, Technical Program Committees, and as session chairs of many IEEE conferences include International Microwave Symposiums and IEEE Antennas and Propagation Symposium. Dr. Wang was a recipient of IEEE Region 3 Outstanding Engineer Award in 2018, NSF Early Faculty Development (CAREER) Award in 2012, USC Breakthrough Star Award in 2016, multiple IBM Invention Achievement Awards, NASA Tech Brief Award, and Young Faculty Development Award from Southeastern Center for Electrical Engineering Education.

Wang's presentation slides >>>

9:40 - 11:10

Workshop 1  Main room

Keysight/ADS Workshop

Power Integrity Simulation and Measurement Tips and Tricks

Heidi Barnes, Senior Applications Engineer, Keysight Technologies

Abstract: Power integrity is the foundation to signal integrity. Learn how to leverage the latest in time domain and frequency domain measurements and simulation to deliver quiet power to modern day high speed digital loads. See how easy it is to simulate Conducted EMI with modern EM tools and see how to use real-time transforms of measured data to find crosstalk noise sources.
Speaker Bios: Heidi Barnes is a Senior Application Engineer and Power Integrity Product Owner for High Speed Digital applications in the Design Engineering Software Group of Keysight Technologies. Her recent activities include the application of electromagnetic, transient, and channel simulators to solve signal and power integrity challenges.  Author of over 20 papers on SI and PI, active member in developing the new IEEE P370 Standard involving interconnect S-parameter quality after fixture removal, and recipient of the DesignCon 2017 Engineer of the Year.  


Barnes' presentation slides >>>

Workshop 2 

De-embedding and compliance automation solutions for accurate performance verification of high-speed digital interconnects

Eric  Oseassen, Application Engineer, Rohde & Schwarz

Abstract: Each new generation of high-speed physical layers demands higher bandwidth and smaller vertical eye opening, across multiple lanes, to achieve impressive data rates.
Characterizing the interconnect channel between TX and RX is vital when designing products for such high data rates, but test fixture considerations and multiple transmission paths can make the process complex and time consuming.
Additionally, this paper will provide an update on the evolution and performance requirements of IEEE 802.3 interconnects up to IEEE 802.3ck (100Gbps per lane) and will introduce new automated workflows for data collection of these high-speed multi-lane interconnects, including data collection and calculation of Channel Operating Margin (COM) and Effective Return Loss (ERL) metric.

Speaker Bios: Eric is an application engineer Rohde & Schwarz America. He holds a BSc from the City College of New York and an MSc from NYU Polytechnic. Eric has served in several roles, including R&D for the Aerospace community, Field Applications and Remote Sensing Development. Eric He is a plank-owner at two startup companies in the early aughts. His core interests include Amplifier and Converter Design & Characterization and Signal Integrity issues

11:15 - 12:15

Some 200 Gb/s per Lane Challenges

Mr. Richard Mellitz, Distinguished Engineer, Samtec

Abstract: Perhaps if we could bring Ralph Hartley and Claude Shannon into our time, we might get advice about information capacity only being limited ability our ability distinguish a signal from noise. Then we might deduce that our information bandwidth is only limited by the ratio of signal to noise (SNR). The caveat is context.  Some might argue that power and latency are contributing factors as well.  There would be little effort required for signaling to move from 100 Gb/s to 200 Gb/s if everything scaled. However physical material and manufacturing, although improving, is not scaling by a factor of 2. There is another constraint. The size of system enclosures seems to be a relative constant across the decades.  Modulation strategies are endemic for 200 Gb/s and not without debate. Amplitude modulation can help but that comes at the expense of SNR which can be improved with error correction and complex equalization. Error correction comes at the expense of latency and complex equalization comes at the expense of power. Keeping modulation constant results in a doubling of the sampling rate and decreasing the symbol window from 18 ps to 9 ps. This but does not come without problems. The same can be said about s-parameter frequency domain acquisitions.  The discussion will pick on few specific challenges for distinguishing symbols from noise because of the shrinking symbol time and increased frequency bandwidth requirements.

Speaker Bios: Richard Mellitz is presently a Distinguished Engineer at Samtec, supporting interconnect signal integrity and industry standards. Prior to this, he was a Principal Engineer at Intel and Digital Equipment Corp (DEC). 

Richard has been a key contributor to IEEE802.3 electrical standards for many years. He led efforts to develop radically new time specification methods called COM (Channel Operating Margin) and ERL (effective return loss). These are now an integral part of Ethernet and OIF standards. Early in his career he founded and chaired an IPC (Association Connecting Electronics Industries) committee delivering IPC’s first PCB loss test methods as well as authoring the industry’s’ first TDR (time domain reflectometry) standard. Richard holds many patents in interconnect, signal integrity, design, and test. He has delivered numerous signal integrity papers at electronic industry design conferences and for past 10 years have averaged a dozen or so presentations per year at IEEE and OIF standards meeting. Richard received the IEEE Standards Association Medallion and the Intel Achievement Award (IAA). The IAA was for spearheading the efforts to creating on of the industry’s first graduate signal integrity program at University of South Carolina.

Mellitz's presentation slides >>>

12:30 - 1:30

Low-cost Signal Integrity Solutions

Dr. Eric Bogatin, Professor of EE, University of Colorado, Boulder

Abstract: At the University of Colorado, Boulder, one research program in our High-Speed Digital Engineering Group focuses on finding or developing low-cost solutions to SI problems. In this presentation, I will review five of our solutions. These will a quick review of some of the free simulation tools anyone can access, a $5, 5 Gbps PRBS source, a 35 cent, 10 GHz bandwidth SMA launch, a $600 VNA for low impedance PDN measurements and a $60 method for in situ scope bandwidth measurements. Not all useful signal integrity solutions need to be costly.

Speaker Bios: Since Jan 2021, Dr.  Eric Bogatin has been a full time professor in the ECEE department teaching the Practical PCB Course and the Senior Design Capstone Course. In addition, he is involved with research activities related to signal integrity and circuit design and analysis, collaborating with other faculty and involving graduate and undergraduate students. 

He is the technical editor of the Signal Integrity Journal, one of the few industry-focused publications that covers signal integrity, power integrity and electromagnetic compliance topics.  Prof. Bogatin is also a Fellow with Teledyne LeCroy and continues to offer webinars and presentations on best measurement practices using real time scopes, TDR and VNA instruments. As part of his Fellow actives, he is the Dean of the Teledyne LeCroy Signal Integrity Academy.

Prof. Bogatin received his BS in physics from MIT in 1976 and MS and PhD in physics from the University of Arizona in Tucson in 1980. In his graduate work, he focused on lasers, quantum optics and desktop experiments on special relativity and cosmology using frequency stabilized lasers.

For the next 40 years, he worked in industry in senior engineering and management positions at Bell Labs, Raychem, Sun Microsystems, Ansoft and Interconnect Devices. He has written 18 technical books about signal integrity and electronics and lectures on signal integrity topics worldwide.

Bogatin's presentation slides >>>

1:45 - 2:45

Data Rate Scaling for Backwards Compatible HVM Interconnect

Dr. Mohiuddin Mazumder, Senior Principal Engineer, Intel Corporation

Abstract: Innovations in circuits and channels such as jitter and power scaling, improved equalization, and signal modulation schemes are pushing the signaling data rate to 200+ Gigabit/s (Gb/s). Such high data rates were deemed impossible just a few generations ago. Although many enablers for such breakthroughs are essential for technology advancement, not all of them can be used in interconnects such as Peripheral Component Interconnect Express (PCIe). The requirements of backwards compatibility, High Volume Manufacturing (HVM) capability, low latency, low power, and acceptable cost impose constraints on the HVM-implementable circuit and channel solutions. In this presentation, we will discuss a few example scenarios: (1) improvements in connectors, systems, and cards to ensure backwards compatibility for PCIe data rate scaling from 2.5 Gb/s to 64 Gb/s over six generations, and (2) improvements in PCIe electrical, logical, and protocol layers to keep PHY latency increase in 64 Gb/s PAM4 over 32 Gb/s NRZ solution within a few nanoseconds for a x16 link. We will share our key experiences and highlight the need for collaboration across disciplines such as electrical, logical, protocol, mechanical, reliability, and manufacturing as well as across companies in the ecosystem with deep expertise in design and manufacturing of processors, systems, cards, connectors, cables, and PCBs to develop backwards compatible HVM solutions.

Speaker Bios: Dr. Mohiuddin Mazumder is a senior Principal Engineer in the Data Center and AI division of Intel. He leads the electrical pathfinding and development of electrical specifications for I/O standards such as Peripheral Component Interconnect express (PCIe), Compute Express Link (CXL), and Intel’s UltraPath Interconnect (UPI) used for connecting processors with high-speed components. Mohiuddin currently co-chairs the Electrical Work Group of PCI-SIG, an industry consortium of about 900 companies, that delivers specifications for components to enable fast, efficient data transfers between processors and peripheral devices. He has been leading the development of electrical specification of UPI, a coherent CPU-to-CPU interconnect, since its introduction, and it is used in all Intel multi-CPU based server platforms. Through his leadership in PCI-SIG and strong collaboration with industry partners, Mohiuddin has been driving improvements in circuits and channel components necessary to double the PCIe bandwidth every generation and PCIe is now in its sixth generation with full backwards compatibility. He also leads the development of various high-speed measurement methods to support the PCI-SIG compliance program. Mohiuddin has been awarded the PCI-SIG DevCon 2021 Chairperson’s Award for his technical contributions to the expansion of PCIe technology over the years.

Mohiuddin Mazumder received his B.S. degree in Electrical Engineering from Bangladesh University of Engineering and Technology in 1989, his M.S. degree in Electrical Engineering from New Mexico State University in 1992, and his Ph.D. degree in Applied Physics from Yale University in 1996. 

Mazumder's presentation slides >>>

2:50 - 4:20

Workshop 3 (Main Room)

Optimizing PCB Design and Analysis for 112G High Speed Connector Interfaces

Dr.  Kai Du, Sr Principal Product Engineer, Cadence 

Abstract: As 112G+ connectors are used in more applications, PCB Design teams will face the challenge of optimizing the interface between high-speed connectors and PCBs with varying stackups and varying route density that can create crosstalk on high-speed signals.  Design teams need to look at this problem in its entirety with highly accurate 3D FEM field solvers.  This requires speed, capacity, and efficient memory consumption that has not traditionally been available to users of 3D FEM tools.  This workshop will go through a workflow using Cadence Allegro PCB Designer and Cadence Clarity 3D Solver that addresses the challenges and reduces engineering time in optimizing high-speed connector interfaces.


  • Clarity 3D Solver overview
    • Merging mechanical connector models with PCB (electrical) designs
    • Protecting connector vendor IP through encryption
    • Reducing error-prone re-drawing of 3D FEM optimized structures by PCB Design Teams through eXML back annotation

Speaker Bios: Dr. Kai Du is a product engineer at Cadence. He obtained a PhD in engineering science and mechanics from the Pennsylvania State University. He has over 20 years of experience in high frequency EDA tools, working on both R&D and customer support.

Workshop 4

Antenna placement in a complex environment to analyze the Electromagnetic interference (EMI) resulting from the effect of the platform and coexistence of radiating source(s).

Dr. Kapil Sharma and Enow Tanjong, CST of America

Abstract: Electromagnetic interference mitigation arising due to the effect of the platform and coexistence of radiating sources in critical infrastructure systems has become an imperative and challenging task for SI and EMC engineers.  Different case studies on interference analysis are presented to showcase the effectiveness of SIMULIA CST Studio Suite in accurately modeling such scenarios. We discuss the challenges of characterizing complex electromagnetic environments, emulating these environments in the simulations, and correlating with test methods that adequately evaluate the ability of a device to perform in that environment. We also address current electromagnetic compatibility and coexistence standards, and suggest future research work needed to update or develop interference and coexistence simulation techniques for wireless devices and systems.

Speaker Bios: Dr. Kapil Sharma is currently an application engineer with Dassault Systemes Simulia CST group where he is involved in providing technical support related to EMC, SI/PI, and ESD analysis to several clients in the North American region. He received the M.S. and Ph.D. degrees in electrical engineering from The Pennsylvania State University, State College, PA, USA, in 2013 and 2017, respectively.  He has presented at several IEEE conferences and symposia for the past 10 years, and is actively involved in different research areas related to computational electromagnetics, SI/PI, and EMC analysis. His current research interests include numerical electromagnetics, signal integrity and electromagnetic compatibility analysis of high-speed interconnects, electromagnetic characterization of materials, optimization algorithms, and parallel computing.

Enow Tanjong is currently a Senior Solution Consultant with Dassault Systèmes Simulia where he serves a lead technical role in supporting pre-sales efforts for Value Solution Clients and Partners. He has over 12 years of experience in the simulation software industry gained after receiving a B.Sc. Magna and M.Sc. in Electrical Engineering from the University of Massachusetts. His graduate studies involved the numerical and experimental electromagnetic analysis (modeling) of complex metallic radiating structures.

Sharma's presentation slides >>>